This post is a part of the series on audio amplifier feedback. The contents of the series can be found here.

So far in this series of posts, I have been looking at shaping the loop gain of an amplifier by modifying its forward gain $A$:

Although I only scratched the surface of that topic, let me move to the gain of feedback network $B$.

Consider a hypothetical amplifier from my

earlier post with three poles at 1kHz, 1MHz and 20MHz inside a feedback loop setting the ideal closed loop gain at 20dB:

As discussed in

that post, the amplifier's accumulates just under 180 degrees of phase lag at the frequency where the loop gain is unity (crossover frequency), its phase margin is close to zero, and the amplifier is on the verge of becoming a generator:

Connect a small capacitor in parallel to the feedback resistor:

Although the forward gain (

**green** curve) does not change, the ideal closed loop gain (the inverse of the feedback network's gain,

**blue** curve) now has a kink:

Compare the loop gain with (

**brown** curve) and without (

**red** curve) the capacitor:

The capacitor extends the bandwidth from 4.4MHz to 6.7MHz and improves the phase margin from zero to 43 degrees. This is called **lead compensation**. Intuitively, the capacitor "speeds up" the feedback loop - extends its bandwidth and compensates some of the phase lag introduced in the forward path $A$.

Unlike dominant pole (e.g. Miller) compensation, lead compensation does not affect the loop gain at low frequencies, so there is no tradeoff between stability and loop gain, definitely a positive. On the other hand, where dominant pole compensation decreases the amplifier's bandwidths, lead compensation extends it, which may be problematic. As the zero-loop-gain frequency increases, high frequency poles add to the phase lag, the impact of parasitics increases, the variations in the parameters of parts with voltage and current become more important, the construction of the amplifier requires more attention, and so on.

Textbooks say that the properly placed zero should cancel one of the amplifier's poles. The reality is more complex. First, lead compensation only works when the crossover frequency (where the loop gain become unity) occurs between the pole and the zero:

That is, the value of the lead compensation capacitor cannot be chosen arbitrarily. While increasing the Miller compensation capacitor always improves stability (at the cost of reduced loop gain), the lead compensation capacitor must have just the right value. Too much or too little won't improve the phase margin. In addition, too large a capacitor will still extend the bandwidth, bringing all the associated costs but no benefits of better stability.

Second, in a real circuit, selecting the value of the compensation capacitor is even more difficult because the forward gain and the crossover point are not fixed. With the signal, the parameters of various components change, the crossover point moves, and the lead compensation may become ineffective.

Third, a limitation specific to the lead compensation with a single capacitor is that, for a given closed-loop gain, the pole and the zero cannot be placed independently: $${\omega_p \over \omega_z}={{R_1 C}\over{(R_1 || R_2)C}}={R_1\over{R_1 || R_2}}={{R_1+R_2} \over R_2}={1+{R_1 \over R_2}}$$

That is, the zero and the pole are separated by a factor equal to the amplifier's ideal closed loop gain at DC as set by the feedback network. For an amplifier with 20dB gain, the pole will always be a decade higher than the zero. This fixed relationship is not always convenient.

The workaround for that last problem is to add a resistor in series with the capacitor:

The loop gain becomes $$LG=A {R_2 \over {R_1+R_2}}{{s (R_1 + R_3) C + 1} \over {s(R_1 || R_2 + R_3)C+1}}$$ and allows placing the zero and pole independently. In this example, the capacitance was decreased slightly to keep the zero at 2.85MHz, but the pole now is at 15MHz, not 28.5MHz as before.

Another version places the resistor differently:

but achieves a similar result: $$LG=A {R_2 \over {R_1+R_2+R_3}}{{s R_1 C + 1} \over {s(R_1 || (R_2 + R_3))C+1}}$$ Here a slightly higher capacitance was chosen to compensate for the smaller $R_1$ and keep the zero at 2.85MHz. The pole is at 14.3MHz.