## Tuesday, September 6, 2022

### High Precision Composite Op-Amps, Part 2

This post is a part of the series on audio amplifier feedback. The contents of the series can be found here.

My previous post on this topic was on composite opamps from by John D. Yewen's article "High-precision composite op-amps" (Electronics & Wireless World, February 1987):

Appropriately choosing the voltage divider R1R2 at the output of U1 allows to improve stability (phase margin) of the composite at the expense of the loop gain. Here, orange traces are the loop gain of the composite from the schematic above, while blue are the maximum possible loop gain with the same two opamps:

For audio applications, it is desirable to maximize the loop gain, at least in the audio band, but preserve the phase margin. To achieve that, let me look at the role of the voltage divider in Yewen's composite.

Referring to the schematic above, U2 sees a (differential) input signal that is a sum of (i) the signal at the non-inverting output, where Ri and Rf connect, and (ii) the same signal amplifier by U1 and divided by R1R2.

At low frequencies, U1's gain is large, and U2's input signal is effectively that at its non-inverting input. The loop gain is the product of that of U1 and U2 and falls with frequency at 40dB/decade. At high frequencies, U1's gain is small, and U2's input signal is effectively that at its inverting input. The loop gain is just that of U2, falling at 20dB/decade.

The transition from "low" to "high" frequencies is a zero in the composite's loop gain, located at the frequency where the signal magnitudes at the non-inverting and inverting inputs of U2 are equal - that is, when the gain of U2 followed by R1R2 is unity. For a single-pole U1, that frequency is a fraction of U1's Gain Bandwidth Product (GBW):$$F_{zero}=GBW_{U_1} \times {R_2 \over {R_1+R_2}}$$That is, Yewen's voltage divider sets the frequency of a zero in the composite's loop gain. In the example above, GBW is 10MHz, the divider's attenuation is 22, so the zero is at ${{10 MHz}\over 22} = {455 kHz}$.

One way to keep that zero and maximize the loop gain at low frequencies is to make the voltage divider frequency dependent, for example:

Adding an inductor in parallel to R3 adds a pole-zero pair (disregarding the inductor's own series resistance, the pole is at $F_p={1 \over {2 \pi}} {{R_3 || R_4} \over L_1}$, the zero at $F_z={1 \over {2 \pi}} {R_3 \over L_1}$). With the values shown, we get about 12dB of extra loop gain at 20kHz with the same phase margin as without the inductor:

A 22mH inductor may not be very practical, but a similar effect can be achieved with a capacitive divider:

Here, the pole is at $F_p={1 \over {2 \pi R_5 (C_1 + C_2)}}$, the zero at $F_z={1 \over {2 \pi R_5 C_2}}$. With the values shown, the loop gain is about the same as with the inductor above:

Not bad for one additional passive component. It works in hardware, too, although you may need to add a resistor in series with U5's output to isolate it from capacitive load. R5 can be adjusted for optimal stability and clipping.

Can we make it still better? Yes we can! Stay tuned...